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3.3.3
V BUF , V REG , and V REGA Capacitance Monitor
A monitor circuit is incorporated to ensure predictable operation if the connection to the external V BUF , V REG , or V REGA , ca-
pacitor becomes open.
In asynchronous mode, the V BUF regulator is disabled t CAPTEST_ADLY seconds after each data transmission for a duration of
t CAPTEST_TIME seconds. If the external capacitor is not present, the regulator voltage will fall below the internal reset threshold,
forcing a device reset.
In synchronous mode, the V BUF regulator is disabled t CAPTEST_SDLY seconds after each sync pulse for a duration of
t CAPTEST_TIME seconds. If the external capacitor is not present, the regulator voltage will fall below the internal reset threshold,
forcing a device reset.
The V REG and V REGA regulators are disabled at a continuous rate (t CAPTEST_RATE ), for a duration of t CAPTEST_TIME seconds.
If either external capacitor is not present, the associated regulator voltage will fall below the internal reset threshold, forcing a
device reset.
I DATA
CAP_Test
V BUF
t CAPTEST_TIME
Capacitor Present
t CAPTEST_ADLY
Capacitor Open
V BUF_UV_f
POR
Time
Figure 10. V BUF Capacitor Monitor - Asynchronous Mode
V CC
CAP_Test
V BUF
t CAPTEST_TIME
t TRIG
t CAPTEST_SDLY
V BUF_UV_f
Capacitor Present
Capacitor Open
POR
Time
Figure 11. V BUF Capacitor Monitor - Synchronous Mode
MMA52xxKW
Sensors
22
Freescale Semiconductor, Inc.
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